DFT Engineer
Bengaluru · Mid Level
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Job description
We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.
Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.
If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.
Looking forward to seeing many of you take this step.
Texas Instruments is seeking a talented and passionate DFT Engineer to join our silicon design team. In this role, you will be responsible for ensuring the testability and quality of TI's next-generation semiconductor devices. You will collaborate with cross-functional teams spanning design, physical design, and product engineering to deliver high-quality, silicon-proven test solutions.
This is an exciting opportunity to work on low cost MCUs using industry-leading EDA tools in a collaborative and innovation-driven environment.
Responsibilities
- Develop and execute DFT architecture and scan insertion strategies for low cost MCUs
- Implement and validate ATPG test patterns to achieve automotive grade fault coverage
- Design and deploy Memory BIST (MBIST) solutions for embedded memories across SoC designs
- Ensure DFT rule compliance throughout the design flow from RTL to tape-out
- Debug and resolve complex ATPG, scan, and Gate-Level Simulation (GLS) violations
- Perform DFT sign-off checks and ensure test coverage meets product quality targets
- Develop and maintain Tcl, Perl, and Python scripts to automate DFT flows and improve efficiency
- Continuously improve DFT methodologies, flows, and best practices within the team
Qualification
- Experience with scan compression techniques (e.g., Modus EDT/IJTAG)
- Familiarity with IEEE 1149.1 (JTAG) / IEEE 1500 standards
- Exposure to low-power DFT methodologies (clock gating, power domain testing)
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