Senior ASIC Design Engineer

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

Work as part of a world class ASIC design team, building leading edge chips for the Coherent Optics market.

Role:

In this role you are expected to work with architects to understand the requirements, document them and implement the functional block or an IP.

What you will be doing:

• Work closely with Architects to understand the requirements, document them, and implement the functional block or an IP

• Capture the design intent, uArch, RTL coding, API coding, lint, constraints development, CDC, and synthesis

• Debug the designs and work with verification team members to get a functionally clean block

• Integrate blocks and create physical design blocks for place and route

• Work with Physical Design team to ensure that the design meets area, timing, power requirements

• Test their design block in the lab and work with lab validation team members

What we seek:

• Ability to abstract complex functions

• Ability to do the uArch using block diagrams, waveforms and mathematical and logical models/equations

• Good understanding of use of FIFOs, state machines

• Exposure to RTL coding using Verilog/system Verilog

• Good logic design skills with ability to understand timing, area and power reports

• Experience in timing constraints development, running lint and CDC checks, synthesis using ASIC or FPGA tools

• Interested in using assertions and formal property verification to develop bug free designs

• Experience of 5+ years in design (uArch, RTL coding, RTL checks and debug)

Preferred: Prior experience in Ethernet/Networking domain