Job description

RTL Design Engineer (4+ Years)

Location: Electronic City, Bangalore

Company: Sanlayan Technologies

Job Summary

Sanlayan Technologies is seeking an RTL Design Engineer with 4+ years of

experience to develop high-performance FPGA-based digital systems for radar,

electronic warfare (EW), communication, and high-speed data acquisition platforms.

The role involves designing synthesizable RTL for FPGA platforms, implementing

real-time digital signal processing (DSP) pipelines, and integrating high-speed data

converter interfaces and streaming architectures. The engineer will be responsible

for translating signal processing algorithms into efficient FPGA implementations

optimized for latency, throughput, and resource utilization.

The candidate will collaborate closely with algorithm, hardware, embedded software,

and system engineering teams, contributing across the complete FPGA development

lifecycle, including RTL design, simulation, FPGA implementation, hardware bring-

up, and system validation.

Responsibilities

 Design and implement synthesizable RTL using Verilog, SystemVerilog, or

VHDL.

 Develop high-performance DSP pipelines for real-time signal processing

applications.

 Implement FPGA-based signal processing modules such as: FFT

architectures, CFAR detection, Digital filtering, Data buffering and streaming

architectures

 Integrate high-speed ADC/DAC interfaces using JESD204B protocols.

 Design and implement AXI and AXI-Stream based data interfaces.

 Work with high-speed interfaces including: DDR memory interfaces, PCIe,

Ethernet

 Develop testbenches and perform RTL simulations and functional verification.

 Support FPGA synthesis, place-and-route, and timing closure activities.

 Perform FPGA hardware bring-up, debugging, and validation on prototype

hardware.

 Collaborate with algorithm, hardware, and embedded software teams to

integrate DSP pipelines into system-level architectures.

 Participate in design reviews, architecture discussions, and performance

optimization activities.

 Develop and maintain RTL documentation, interface specifications, and

design reports.

Required Qualifications & Skills

Education

B.Tech / M.Tech in Electronics & Communication Engineering, Electrical

Engineering, or VLSI Design.

Experience

Minimum 3+ years of hands-on experience in RTL design for digital signal

processing systems interfacing with high-speed ADC and DAC devices.

Technical Skills

 Strong experience in RTL design and development.

 Proficiency in Verilog / SystemVerilog / VHDL.

 Knowledge of synthesizable RTL coding practices and FPGA design

methodologies.

 Experience working with JESD204B data converter interfaces.

 Knowledge of AXI / AXI-Stream protocols.

 Experience integrating DDR memory interfaces.

 Familiarity with PCIe and Ethernet interfaces (preferred).

 FFT architectures, CFAR detection, Digital filtering, Data framing and high-

throughput streaming pipelines

 Xilinx Vivado, Simulation tools such as ModelSim, QuestaSim, or Xcelium

 Experience with FPGA bring-up and hardware debugging.

 Interface validation with ADC/DAC hardware and high-speed data converters.

Key Competencies

 Strong digital architecture and RTL design capability.

 Ability to translate signal processing algorithms into efficient FPGA

implementations.

 Strong understanding of high-throughput streaming architectures and dataflow

design.

 Experience debugging complex FPGA-based systems.

 Ability to analyze timing constraints, resource utilization, and performance

trade-offs.

 Strong problem-solving and analytical thinking.

 Good documentation practices and design review participation.

 Ability to work effectively within cross-functional engineering teams.

 Strong ownership and accountability for design quality, performance, and

delivery.

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