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Cadence Design Systems

Lead Software Engineer

Noida · Senior

Recently posted - highest visibilityVerified listingPosted 18h ago

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Skills required

9 listed
Electronic DesignIntelligent SystemsDesign StrategiesFormal VerificationVerilogSystemVerilog (Direct Programming Interface)Electronic Design Automation (EDA) SoftwarePython (Programming Language)+1 more
Electronic DesignIntelligent SystemsDesign StrategiesFormal VerificationVerilog

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Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and healthcare.

 

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

 

Job Summary

In this role, you will independently own the design, development, validation, and delivery of Formal Verification IPs, including Verilog design models and SystemVerilog Assertions for industry-standard protocols.

 

 

Job Responsibilities:

  • This role involves the design, development, and delivery of Assertion-Based Verification IPs for industry-standard protocols, with ownership of technical execution and quality.
  • Analyze protocol specifications and translate requirements into robust formal verification plans, design models, SystemVerilog Assertions, assumptions, and coverage.
  • Own the end-to-end development and maintenance of Assertion-Based Verification IPs, including architecture, implementation, validation, regression, release readiness, and documentation.
  • Develop synthesizable RTL and verification components using strong RTL design, synthesis, and SystemVerilog concepts.
  • Apply formal verification methodologies to prove complex protocol and design properties, identify convergence challenges, and implement effective abstractions and constraints.
  • Create verification plans, define measurable coverage goals, review results, and drive closure of functional and formal coverage gaps.
  • Debug complex design and verification failures using EDA tools, perform root-cause analysis, and deliver high-quality, scalable solutions.
  • Build and enhance automation, regression, and productivity flows using scripting languages such as Python and Tcl.
  • Provide technical guidance through design and code reviews, mentor junior engineers, and contribute to verification methodology and process improvements.
  • Collaborate with Application Engineering teams and geographically distributed teams to resolve technical issues and meet delivery commitments.
  • Communicate technical risks, dependencies, progress, and recommendations clearly to stakeholders, and support customer-facing technical discussions when required.
  • undefined 

  • Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics 

  • Experience and Technical Skills Required

  • 5+ years of experience in RTL design/Verification in case of BE/BTECH or Masters Degree with 3+ years of experience.

  • Verilog/SystemVerilog and SVARTL design or verificationFormal verification concepts and tools would be plus point.

  • Verification planning and coveragePython/Tcl scriptingAt least one protocol such as AXI, CHI, PCIe, or CXLWorking knowledge of AI/ML concepts and experience using AI-assisted tools to improve verification, debugging, automation, or engineering productivity.  

  • Behavioral skills requiredMust possess strong written, verbal and presentation skills.Ability to establish a close working relationship with both customer peers and management.Explore what’s possible to get the job done, including creative use of unconventional solutions.Demonstrate strong ownership, sound technical judgment, and the ability to drive complex assignments independently from planning through delivery.undefined

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Applicants who checked fit first are 3.1× more likely to hear back

Your match scoreFree · sign in
86Overall
64Skills
97Experience

Your score for this role already exists

ASAI compared this JD against 41 signals - skills, seniority, domain, stack overlap etc. Add a resume and it unlocks in about 30 seconds.

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Free · no signup

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Why people use ASAI

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  • Scored, not searched. Every role ranked against your actual profile.

  • Alerts as often as hourly. Reach new roles while the pile is still small.

  • Skill gaps, spelled out. See exactly which requirements you don't meet yet.

  • Verified jobs, only. Say no to ghost jobs. Your time deserves respect.

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