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HCLTech

Senior Design Lead - Design Validation

Chennai · Staff/Principal

Good timing - competition is buildingVerified listingPosted 11d ago

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64Skills
97Experience

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Skills required

14 listed
Writing SystemsCode CoverageDigital LogicState MachinesC (Programming Language)SystemVerilog (Direct Programming Interface)NetlistPerl (Programming Language)+6 more
Writing SystemsCode CoverageDigital LogicState MachinesC (Programming Language)

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Job description

Job Summary

Define ASIC/SoC verification strategy
Full chip testplan development
Full chip TB Architecture definition
UVM based testbench development
SV functional coverage, Assertions coding
C based TB development
Test case development, coding, execution, bug analysis
Gate Level Simulation
Regressions, coverage analysis
participate in verification closure

Key Responsibilities

Good understanding of ASIC/SoC life cycle
Has participated in multiple ASIC/SoC verification till  tapeout stage
Experience writing ASIC/SoC testplans
"1.Experience in ASIC/SoC Testbench definition
2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."
"1.Expertise & hands-on experience in OVM/UVM methodologies using SV
2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans."
"1. Experience in developing TB components for SOC with C, SV
"
"1. Experience in developing TB components, including functional coverage implementation and assertion coding
2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
4. Experince in SOC C based tests coding & debugging"
"Experience in Gate level simulation & netlist debugging
"
"Exeprince in regression failure analayiss
Functioncal and Code Coverage closure"
Experience in Perl/Shell scripting

Skill Requirements

Languages: Proficiency in Verilog, SystemVerilog, and core concepts of UVM.
Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts. 

EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi). 
"Protocols: 

Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."
Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.

Other Requirements

Education Degree:

" Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), 
Electrical Engineering (EE), VLSI Design, or a closely related field"

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Applicants who checked fit first are 3.1× more likely to hear back

Your match scoreFree · sign in
86Overall
64Skills
97Experience

Your score for this role already exists

ASAI compared this JD against 41 signals - skills, seniority, domain, stack overlap etc. Add a resume and it unlocks in about 30 seconds.

Always free · no credit card · 1 tap with Google

Free · no signup

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Why people use ASAI

Someone shared one job with you. ASAI keeps finding the rest.

  • Scored, not searched. Every role ranked against your actual profile.

  • Alerts as often as hourly. Reach new roles while the pile is still small.

  • Skill gaps, spelled out. See exactly which requirements you don't meet yet.

  • Verified jobs, only. Say no to ghost jobs. Your time deserves respect.

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