Technical Architect - SoC, Verilog, UVM, C, C++

Job Summary

Job Summary

We are seeking skilled Design Verification (DV) Engineers to validate complex ASIC/SoC/IP designs. The role involves developing scalable verification environments, creating test plans, and ensuring functional correctness through advanced verification methodologies such as UVM.

You will work closely with design, architecture, and physical design teams to deliver first-time-right silicon.

Key Responsibilities

Key Responsibilities

• Develop and execute comprehensive verification plans based on design specifications
• Build and maintain SystemVerilog/UVM-based verification environments
• Create reusable testbenches, agents, scoreboards, and checkers
• Develop directed and constrained-random testcases
• Perform functional, code, and assertion coverage closure
• Debug failures and root-cause issues across RTL, testbench, and tools
• Develop and integrate assertions (SVA) and formal checks where applicable
• RTL as well as Gate level simulations
• Automate regression flows and improve verification productivity

Skill Requirements

Technical Skills

• Strong expertise in SystemVerilog
• Hands-on experience with UVM (Universal Verification Methodology)
• Experience with functional coverage, assertions (SVA), and constrained random verification
• Familiarity with EDA tools (e.g., VCS, Verdi)
• Experience in debugging RTL and simulation issues
• Understanding of protocols such as AXI, AHB, APB, PCIe, or similar

Programming/Scripting

• Proficiency in Python/Perl/Shell scripting for automation

Other Requirements

Preferred Qualifications

• Experience in UCIe protocol
• Experience in verifying mixed signal (analog + digital) IPs

Education

• B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent

Soft Skills

• Strong analytical and debugging skills
• Good communication and cross-functional collaboration
• Ability to work in a fast-paced, tapeout-driven environment