Senior Group Technical Architect

Job Summary

Candidates with minimum 15 years' experience is mandatory 

Define ASIC/SoC verification strategy:     

Good understanding of ASIC/SoC life cycle 

Full chip test plan development: 

Has participated in multiple ASIC/SoC verification till tape-out stage 

Full chip TB Architecture definition     

Experience writing ASIC/SoC test plans 

UVM based testbench development     

1.Experience in ASIC/SoC Testbench definition 

2.Experience to Build and maintain reusable block-level and sub-system testbenches using System Verilog and the Universal Verification Methodology (UVM)." 

SV functional coverage, Assertions coding     

1.Expertise & hands-on experience in OVM/UVM methodologies using SV 

2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. 

C based TB development     

1. Experience in developing TB components for SOC with C, SV 

Test case development, coding, execution, bug analysis     

1. Experience in developing TB components, including functional coverage implementation and assertion coding 

2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic. 

3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues. 

4. Experience in SOC C based tests coding & debugging 

Gate Level Simulation     

Experience in Gate level simulation & netlist debugging 

Regressions, coverage analysis     

Experience in regression failure analysis, Functional and Code Coverage closure 

Own and execute verification closure     

Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files. 

Experience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently. 

Experience in Document test plans, micro-architecture specifications, and verification results for team reviews 

Key Responsibilities

Experience to lead the micro-architecture and full-chip verification of our next-generation semiconductor products 

End-to-end ownership of complex IPs and subsystems, from defining functional specifications to managing final tape-out sign-off. You will architect robust, scalable UVM environments, solve critical architectural bottlenecks, and mentor a team of engineers to ensure first-pass silicon success 

Engineering Execution     

Develop complex verification components, including bus functional models (BFMs), monitors, predictors, and highly parameterized scoreboards. 

Oversee and resolve deep technical issues in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), linting, and formal verification. 

Direct the deployment of advanced verification techniques such as Formal Verification, Hardware Emulation (e.g., Palladium, Zebu), and Power-Aware (UPF/CPF) simulations. 

Management & Strategy     

Act as the primary technical point of contact, interfacing with System Architects, Backend/Physical Design teams, and Post-Silicon Validation teams. 

Provide technical mentorship, code reviews, and career guidance to junior and mid-level design and verification engineers. 

Establish, standardize, and continuously improve engineering methodologies, automation scripts, and best practices across the organization. 

Skill Requirements

Core Technical Skills     

Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs. 

Expert Languages: Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology). 

Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.  

Processor Knowledge: Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable." 

Tools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.  

Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)." 

Scripting: Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking. 

Soft Skills     

Strategic Thinking: Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies. 

Influence: Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.

Other Requirements

EducationDegree:     

Bachelor's or Master's degree in Electronics & Communication Engineering (ECE),  

Electrical Engineering (EE), VLSI Design, or a closely related field"