Sr. Design Automation Engineer

Description

We are building an intelligent analog and mixed-signal design automation flow that applies agentic AI and machine learning to modernize design and verification practice. You will join a central engineering team developing a next-generation, AI-enabled design and verification platform for complex analog/mixed-signal and RF products and modules - from die-level blocks to integrated module architectures.
This role calls for an engineer who can bring analog/RF IC design and verification knowledge and an automation mindset to encode that expertise into scalable flows. You will inform how the platform reasons about circuits, runs verification, and guides engineers through complex AMS and RF workflows. Your job is to bridge proven AMS/RF practice and new automation so the platform stays grounded in how high-performance products are built and signed off.

Responsibilities

• Understand design, simulate, and layout challenges in RF/analog blocks including PAs, LNAs, switches, and filter networks in Cadence Virtuoso across multiple process technologies and be able to encode that knowledge into an intelligent automation flow
• Understand how design, simulation and physical verification data is generated across distributed platforms and develop strategies for engineering that data for a machine learning and/or agentic AI platform
• Partner with PDK, layout, and verification teams to align design practices with process capabilities, DRM limits, and foundry release schedules
• Develop connections between design steps and tools in the analog, RF and mixed-signal domains using agentic AI framework with the goal of developing a self-evolving design flow

Required Experience and Skills

• B.S. or higher in Electrical Engineering, Computer Engineering, or Computer Science
• 3+ years of professional experience in analog/RF IC design and verification or EDA engineering in an analog or RF environment
• Strong automation skills for analog/RF flows (Python, SKILL, Tcl, or equivalent)
• Demonstrated ability of turning informal design and verification practice into structured workflows
• Strong debugging and analytical skills
• Excellent communications skills with the ability to work and thrive in a team environment

Desired Experience and Skills

• Hands-on Cadence Virtuoso: schematic entry, simulation, layout
• Experience creating and verifying Verilog-A and SystemVerilog RNM behavioral models for analog circuits.
• Automation for flow orchestration, testbench setup, results parsing, or layout-assisted routines
• Exposure to internal/custom process technologies and/or external foundry PDKs for analog/RF work
• Practical ML/AI skills: Python-based development with frameworks such as PyTorch, TensorFlow, or LangChain/LlamaIndex (or equivalent); experience building LLM applications, RAG pipelines, or ML inference services
• Experience building or integrating agentic workflows that call EDA tools (simulation, DRC/LVS, EM, or job schedulers) as tools in a loop
• Working knowledge of agentic AI systems: multi-step agents, tool use / function calling, planning and orchestration, and evaluation of agent behavior — useful on this seat, not the core of it
• Experience with filter co-design in a module environment, EM-aware layout, or AMS co-simulation — useful as domain grounding for automated and agent behavior
• Scripts that integrate with HPC/job farms for batch simulation or regression
• Interest in applying ML to circuit/layout representations (graphs, embeddings) beyond text-only LLM use

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