Sr. Design Automation Engineer

Description

We are building an intelligent analog and mixed-signal design automation flow that applies agentic AI and machine learning to modernize design and verification practice. You will join a central engineering team developing a next-generation, AI-enabled design and verification platform for complex analog/mixed-signal and RF products and modules - from die-level blocks to integrated module architectures.
This role calls for an engineer who has built UVM verification environments and has an automation mindset to encode that expertise into scalable flows. You will inform how the platform reasons about testbenches, coverage, and regressions, and guides engineers through complex digital and mixed-signal verification workflows. Your job is to bridge proven DV practice and new automation so the platform stays grounded in how high-performance products are verified and signed off.

Responsibilities

• Design and deploy ML inference models for engineering use cases: prediction, classification, anomaly detection, and recommendation over design/simulation data
• Build data engineering pipelines to ingest, clean, label, and version datasets from design and layout databases, as well as simulation and physical verification results
• Develop LLM-based applications with chain-of-thought prompting for guided troubleshooting, documentation Q&A, and methodology assistance
• Implement MLOps practices: model versioning, A/B testing, monitoring for drift, and reproducible training pipelines
• Create APIs and services that integrate ML capabilities into existing EDA and engineering platforms
• Collaborate with domain experts to define features, labels, and evaluation metrics grounded in engineering outcomes
• Stay current with industry-standard techniques in deep learning, transformers, and efficient inference

Required Experience and Skills

• B.S. or higher in Electrical Engineering, Computer Engineering, or Computer Science
• 3+ years of professional digital design verification experience
• Strong experience building SystemVerilog/UVM testbenches (architecture, agents, scoreboards, coverage) - not only writing tests in an existing environment
• Strong experience with scripting languages (Python, Bash)
• Strong debugging and analytical skills
• Excellent communications skills with the ability to work and thrive in a team environment

Desired Experience and Skills

• Simulator and regression experience (VCS, Xcelium, Questa, or equivalent) including batch/farm runs
• Assertions (SVA), formal, or mixed-signal / AMS co-verification
• Experience creating, verifying, and simulating with behavioral models for analog circuits.
• Automation for testbench setup, results parsing, coverage reporting, or regression orchestration
• Proficiency with git version control and CI/CD pipelines
• Practical ML/AI skills: Python-based development with frameworks such as PyTorch, TensorFlow, or LangChain/LlamaIndex (or equivalent); experience building LLM applications, RAG pipelines, or ML inference services
• Experience building or integrating agentic workflows that call EDA tools (simulation, formal, job schedulers) as tools in a loop
• Scripts that integrate with HPC/job farms for batch simulation or regression
• Interest in applying ML to verification artifacts (coverage, logs, traces, test stimulus) beyond text-only LLM use

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