At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design and implement a full, dedicated, and flexible (e.g., UVM based) verification environment
Involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of the overall system-level solution.
Defining verification strategy from IP to top digital integration
Define requirements for block level and full-chip level verification infrastructure
Create test plans for unit-level and chip-level verification and post-silicon validation
Debug failures and drive in-time resolution of bugs
Create coverage monitors and drive coverage to required quality targets
Develop tools, test benches, and test suites (UVM, C++/C ) to execute test plans.
Write functional coverage, analyze both code and functional coverage, and close coverage gaps
Develop and use unit level test benches that use functional tests as well as constrained random stimulus.
When needed, define and develop formal verification environment

Skills

BS or MS in EE, CS or related engineering discipline
5-10 years of demonstrated experience in verification of IPs, Digital Design and SoCs
Strong experience in design and verification standards and methodologies (SVA, UVM/OVM).
In-depth knowledge of Verilog and System Verilog HDL and experience with simulators and waveform debugging tools
Solid understanding and experience with verification of Digital Design and SoC architectures including test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).
Strong experience creating test benches and automating regression test suites, preparing, and presenting detailed verification reviews
Knowledge of state-of-the-art EDA tools (e.g., Cadence Xcelium…)
Experience with formal verification is plus.
Programming experience in languages common to the industry (e.g., C, C++, Shell scripting)
Solid scripting skills (Python preferred or Perl or TCL).
Knowledge of test and DFT (Scan insertion, Scan compression, test coverage analysis, ATPG pattern generation, simulation and debug, IEEE 1149.1, 1500 and 1687 standards)

Design and implement a full, dedicated, and flexible (e.g., UVM based) verification environment
Involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of the overall system-level solution.
Defining verification strategy from IP to top digital integration
Define requirements for block level and full-chip level verification infrastructure
Create test plans for unit-level and chip-level verification and post-silicon validation
Debug failures and drive in-time resolution of bugs
Create coverage monitors and drive coverage to required quality targets
Develop tools, test benches, and test suites (UVM, C++/C ) to execute test plans.
Write functional coverage, analyze both code and functional coverage, and close coverage gaps
Develop and use unit level test benches that use functional tests as well as constrained random stimulus.
When needed, define and develop formal verification environment

BS or MS in EE, CS or related engineering discipline
5-10 years of demonstrated experience in verification of IPs, Digital Design and SoCs
Strong experience in design and verification standards and methodologies (SVA, UVM/OVM).
In-depth knowledge of Verilog and System Verilog HDL and experience with simulators and waveform debugging tools
Solid understanding and experience with verification of Digital Design and SoC architectures including test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).
Strong experience creating test benches and automating regression test suites, preparing, and presenting detailed verification reviews
Knowledge of state-of-the-art EDA tools (e.g., Cadence Xcelium…)
Experience with formal verification is plus.
Programming experience in languages common to the industry (e.g., C, C++, Shell scripting)
Solid scripting skills (Python preferred or Perl or TCL).
Knowledge of test and DFT (Scan insertion, Scan compression, test coverage analysis, ATPG pattern generation, simulation and debug, IEEE 1149.1, 1500 and 1687 standards)