Principal Engineer – Design Engineering

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Job Description:

Microchip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems. 

The CBU Product Development team is engaged through the full device R&D cycle from concept, design and implementation stages. Once a prototype is available, we support embedded software development and system validation lab testing through to mass-market production release. We are an experienced chip team working with the latest semiconductor development tools and methodologies in advanced process technologies to develop state-of-the-art network devices.

We are seeking a Principal Engineer in the CBU Product Development team who will be responsible for the design and implementation of digital integrated circuits at the block or top level of a device, solve challenging engineering problems with innovative solutions. You will collaborate with chip architects, subsystem leads and verification team members to deliver increasingly complex designs in a friendly and professional environment.

Responsibilities may include:

·         Contribute to the microarchitecture of communication semiconductor devices in partnership with team leads, mentors and device architects

·         Design digital circuits based on leading-edge industry standards and market requirements

·         Implement designs in System Verilog RTL code utilizing low-power design principles

·         Synthesize designs into logic gates taking advantage of industry-leading tools and flows

·         Provide floor-planning guidance and support to physical design/layout teams

·         Integrate digital and analog circuits with Design-for-Test (DFT) techniques

·         Verify physical timing specifications through Static Timing Analysis (STA)

·         Support of products from Specification through to Production in collaboration with Engineers in Physical Design, Validation, Applications, Software/Firmware, Product Marketing and Production Engineering

·         Develop areas of technical expertise to contribute to the wider team beyond individual deliverables or responsibilities

Requirements/Qualifications:

•      Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering

•      8+ years related experience

•      Excellent analytical and debugging skills and the ability to proactively solve issues

•      Proven ability to thrive on, learn and adapt to new methodologies and technologies

•      Coding expertise in one or more of SystemVerilog/Verilog or VHDL.

•      Experience using one or more of Tcl/Perl/Python, C/C++, XML

•      Excellent verbal and written communication skills in English

•      Experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis.

•      Understanding of physical design interactions, including timing, power, and congestion considerations.

•      Knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.

•      Proficiency in scripting languages such as Tcl, Perl, and/or Awk.

•      Experience with Synopsys or Cadence tool flows for synthesis, verification or STA (an asset)

•      Experience with 28nm and smaller silicon process technologies (an asset)

Travel Time:

0% - 25%

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