We are seeking a highly skilled and motivated Engineer to drive the architecture, development, and implementation of our Soft IP solutions. In this role, you will own the end-to-end FPGA Soft IP development lifecycle—from micro-architecture definition and RTL coding to timing closure, simulation, and physical hardware validation. You will work closely with embedded software, hardware, and systems engineering teams to deliver robust, high-performance FPGA Soft IP solution solutions.

Key Responsibilities

• RTL Architecture & Coding: Define micro-architecture and implement clean, efficient, and reusable RTL code using System Verilog, Verilog, or VHDL.

• IP Integration & Flow Management: Drive the full FPGA tool flow including synthesis, place-and-route (P&R), constraints creation, and static timing analysis (STA).

• Timing Closure: Resolve complex multi-clock designs, Clock Domain Crossing (CDC) anomalies, and timing violations to ensure robust operation.

• Verification & Simulation: Develop testbenches and run block-level behavioral simulations to thoroughly debug and validate logic functionality before target implementation.

• Hardware Bring-up & Debug: Validate RTL functionality on actual evaluation boards using lab equipment like logic analyzers, oscilloscopes, and protocol compliance testers.

• Cross-functional Collaboration: Collaborate with software and board-level hardware teams to establish specifications, interface architectures, and system integration paths.