Technical Staff Engineer-Verification

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Job Description:

Microchip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems. 

The CBU Product Development team is engaged through the full device R&D cycle from concept, design and implementation stages. Once a prototype is available, we support embedded software development and system validation lab testing through to mass-market production release. We are an experienced chip team working with the latest semiconductor development tools and methodologies in advanced process technologies to develop state-of-the-art network devices.

We are seeking a Verification focused Technical Staff Engineer in the CBU Product Development team who will be responsible for the verification strategy and technical leadership of communication semiconductor devices and subsystems. We are looking for an experienced hands-on technical leader who can directly contribute to all aspects of verification from planning, testbench architecture to coverage closure and sign-off readiness at the block and top level of a device. The individual should be to solve challenging engineering problems with innovative solutions and mentor engineers. The individual will be a key member of the CBU’s Silicon Design Center in India with technical leadership and mentoring responsibilities.

Responsibilities may include:

• Verification Architecture and Strategy

• • Own or contribute to verification architecture for leading-edge communications devices

• • Build system-level understanding of device applications and use it to define complete, risk-based verification plans

• • Collaborate with Product Marketing, Applications Engineers, System Architects, Designers and Customers to identify, record, track and verify device requirements

• • Partition verification scope across block, subsystem and device levels, including reusable verification components and coverage models

• • Participate in concept and feasibility studies for next-generation products by identifying verification risks, methodology needs and validation alignment early in the development cycle

• Technical Leadership

• • Lead delivery of verified digital integrated circuits at the device, subsystem or block level as a Verification Architect, Verification Lead or Technical Leader

• • Mentor and provide technical direction to a small team of Verification Engineers

• • Partner with Design Leads and Architects to align implementation intent, verification strategy and sign-off expectations

• • Translate industry standards, market requirements and functional specifications into executable verification plans, coverage goals and measurable closure criteria

• • Develop verification platforms guided by UVM methodology and implemented with SystemVerilog, assertions and reusable verification components

• • Drive verification execution, debug, regression quality, coverage closure and sign-off readiness using industry-leading tools and flows

• Domain Expertise

• • Develop or enhance technical expertise in technologies, verification methodologies, flows or standards

• • Contribute to verification best practices for industry standards such as Ethernet, OTN and related networking technologies

• • Provide subject-matter guidance to development teams within CBU on verification strategy, methodology, debug and closure

• • Enhance internal, proprietary verification flows and practices to improve efficiency, completeness, reuse and sign-off quality

• Cross Functional Responsibility

• • Collaborate with Software, Validation, Applications, Production Engineering and Design teams to deliver production-worthy devices that integrate into a wider system and are supported by robust verification evidence

Requirements/Qualifications:

• Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering
• 12+ years related experience
• Excellent analytical and debugging skills and the ability to proactively solve issues

• Proven ability to thrive on, learn and adapt to new methodologies and technologies

• Strong coding skills

• Experience using one or more of SystemVerilog/Verilog/VHDL, Tcl/Perl/Python, C/C++, XML

• Demonstrated experience verifying complex digital integrated circuits using SystemVerilog, UVM, assertions, constrained-random testing, coverage-driven verification, formal verification or related methodologies

• Excellent verbal and written communication skills in English

• Familiarity with communication protocols such as Ethernet, ASA and others (an asset)

• Experience with Synopsys, Cadence or similar verification, simulation, formal, debug, coverage or regression management tool flows (an asset)

• Experience with state-of-the-art silicon process technologies and complex SoC verification environments (an asset)

Travel Time:

0% - 25%

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