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ASIC Design and STA Engineer
India · Mid Level
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What we know about this role
HIGH
NVIDIA is actively reviewing profiles and moving candidates through the pipeline right now.
First 72 hours
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The first time we've seen this listing - it hasn't been closed and reopened.
Skills required
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Job description
NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!
NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
Take part in top level floor plan and clock planning.
Optimize, together with CAD signoff flows and methodologies.
Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.
Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
3+ years of experience in physical design and STA
Proven experience in RTL2GDS and STA design and convergence
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)
Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required.
Great teammate.
NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!
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