Job description

Role Overview

We are seeking a Lead High-Speed Digital Design Engineer to drive the technical execution of our next-generation hardware platforms. In this role, you will take ownership of the full product lifecycle—from schematic architecture and power/reset analysis to SI/PI simulation, layout guidance, and lab bring-up. You will guide layout resources, establish design workflows, and act as the core technical interface for engineering teams and clients.

Key Responsibilities

Hardware Design & Architecture

Design multi-layer PCBs around high-performance ARM-based Multicore SoCs, RFSOC/FPGA and complex PMIC architectures.
Implement high-speed interfaces: LPDDR4/5, PCIe Gen 4, USB 3.2/4.0, Camera & Display interfaces and 1G/10G/100G Ethernet.
Integrate wireless systems: Wi-Fi 6E/7 and Bluetooth (BT) with RF front-end co-existence routing.

Analysis & Simulation

Model Power-On Reset (PoR) topologies, rail ramp rates, and low-power state transitions.
Perform comprehensive PDN analysis to optimize plane shapes, target impedance profiles, and multi-rail DC IR drops.
Execute detailed Decoupling analysis to determine optimal bulk and ceramic capacitor counts, values, sizing, and cavity placement.
Run SI/PI simulations using any of Ansys HFSS/SIwave, Cadence Sigrity, or Keysight ADS to mitigate crosstalk, reflection, and jitter.

Layout Oversight & Material Trade-offs

Select ultra-low-loss materials (e.g., Megtron, Isola, Rogers, FR4 ) and define advanced PCB stack-ups.
Enforce HDI rules for stacked/staggered microvias, trace width geometries, and capacitor mounting pad/via loops.
Set layout constraints for memory topologies, 1G/10G/100G Ethernet differential targets, and RF via shielding.

Compliance, EMI/EMC & Thermal Engineering

Design for EMI/EMC mitigation from day one, minimizing radiated/conducted emissions and ensuring high immunity.
Own compliance testing for regulatory certifications including FCC, CE etc.. at external test labs.
Validate thermal stability by evaluating board-level power dissipation, checking component junction temperatures, and collaborating on heatsink/thermal interface material (TIM) placement.

Debug, Lab Bring-up , Performance testing & Documentation

Hardware Bring up, Isolate hardware faults using oscilloscopes, VNAs, and logic analyzers.
Coordinate board reworks and execute root-cause analysis (RCA) on prototype failures.
Author technical specs, layout constraint logs, bring-up guides, and hardware errata trackers.
Performance testing and characterization of interfaces /peripherals

Project Leadership & Client Interaction

Lead and guide layout and simulation engineers to ensure strict design compliance.
Establish design workflows, hardware checklists, and rigorous peer review gates.
Scope customer requirements, translate use cases into engineering specs, and present technical trade-offs.

Required Technical Skills

Experience: 4 to 8 years of proven experience in high-speed digital board design and architecture.
Processor Expertise: Practical experience with high-performance ARM-based Multicore SoC architectures.
EDA Tools: High proficiency in Cadence Allegro, Altium Designer, or Mentor Graphics Xpedition.
Regulatory Knowledge: Hands-on experience with EMI/EMC chamber troubleshooting and FCC/CE certification requirements.
Education: Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering.

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