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latticesemi

Senior Design Verification Engineer

Hyderabad · Senior

Older listing - lower visibility likelyVerified listingPosted 79d ago

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Skills required

19 listed
Design VerificationManufacturing OperationsProduct InnovationDesign SpecificationsDigital DesignPower ManagementDraft (Boiler)SystemVerilog (Direct Programming Interface)+11 more
Design VerificationManufacturing OperationsProduct InnovationDesign SpecificationsDigital Design

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Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

Responsibilities:

  • Draft DV scope, strategy & feasibility in response to marketing requirements
  • Develop test plans based on Design Specifications
  • Design & Implement constrained-random testbenches & metrics
  • Code & Execute tests, Debug encountered issues
  • Collate & Analyze test results to closure

Requirements:

  • BS or MS in Computer/Electronics/Electrical Engineering with a minimum of 5 years of relevant design verification experience.
  • Good communication, collaboration & documentation skills.
  • Good grasp of & Hands-on experience with SystemVerilog/UVM, with solid understanding of different available SV/UVM constructs. Experience with languages like Python, make, C, C++ is an advantage.
  • Good analysis & debugging skills. Understanding of HDL & FPGA concepts is an advantage.
  • Experience with industry standard digital design simulators & debugging tools. Experience with Siemens EDA tools specifically is an advantage. Experience with Perforce, Git, Jenkins, & generative AI is also an advantage.
  • Experience in the following technology areas is an advantage: Cryptography, Security, AMBA protocols, SPI, I2C/I3C

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. 


Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit 
www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

 

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Applicants who checked fit first are 3.1× more likely to hear back

Your match scoreFree · sign in
86Overall
64Skills
97Experience

Your score for this role already exists

ASAI compared this JD against 41 signals - skills, seniority, domain, stack overlap etc. Add a resume and it unlocks in about 30 seconds.

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Why people use ASAI

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  • Verified jobs, only. Say no to ghost jobs. Your time deserves respect.

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