Noida · Director
Applicants who checked fit first are 3.1× more likely to hear back
Your score for this role already exists
ASAI compared this JD against 41 signals - skills, seniority, domain, stack overlap etc. Add a resume and it unlocks in about 30 seconds.
Always free · no credit card · 1 tap with Google
LOW
Our tracked job listings for eInfochips show limited recent activity.
First 72 hours
Window passed - posted 596d agoEarly applicants get seen before the pile builds.
Not a repost
The first time we've seen this listing - it hasn't been closed and reopened.
You almost certainly match several of these already. Unlock your skill map to see the matches, the gaps, and what to fix first.
- Functional Area: RTL design, Lower Power Synthesis, Low Power Design, UPF Flow
- 5-20 years of experience in RTL design in Verilog, VHDL
- ASIC/FPGA experience
- If ASIC experience, then Lint/CDC tool experience
- If FPGA experience, then Xilinx or Altera/Intel FPGA parts and tools
- RTL debug experience
- Knowledge of at least one industry standard protocols like I2C/SPI/UART, PCIe, MIPI, AXI, Ethernet
Your match score, skill map and tracker stay free.
Skip jobs with hidden dealbreakers. See what they actually need, what's easy to miss, and how they describe the team.
Ground Reality on every job, plus Insider Path, practice interviews and resume tailoring.
We help you find people there who worked or studied where you did, and draft your first message and follow-up.
Free · no signup
Daily job drops, skill trends and free resources - posted straight to the group. Leave any time.
No spam. Just jobs and resources.
Why people use ASAI
Scored, not searched. Every role ranked against your actual profile.
Alerts as often as hourly. Reach new roles while the pile is still small.
Skill gaps, spelled out. See exactly which requirements you don't meet yet.
Verified jobs, only. Say no to ghost jobs. Your time deserves respect.
More Quality Assurance Engineer roles in Noida
See allKeep browsing