DFT Engineer

Job Summary

We are seeking a highly skilled DFT Engineer to support Qualcomm SoC development programs. The candidate will be responsible for DFT architecture implementation, scan insertion, ATPG generation, MBIST/LBIST integration, pattern validation, and silicon bring-up activities for complex mobile, automotive, and high-performance SoC designs.

Key Responsibilities

DFT Implementation

·        Develop and implement DFT architectures for advanced SoC designs.

·        Perform scan insertion and scan chain validation using industry-standard EDA tools.

·        Integrate and verify DFT features including:

o   Scan Compression

o   EDT

o   MBIST

o   LBIST

o   Boundary Scan (JTAG/IEEE 1149.1)

o   OCC (On-Chip Clock Controller)

ATPG & Pattern Generation

·        Generate ATPG patterns for stuck-at, transition, path-delay, and bridge fault coverage.

·        Analyze fault coverage and optimize pattern count.

·        Debug DRC violations and pattern simulation failures.

Verification & Validation

·        Perform RTL and gate-level DFT verification.

·        Validate scan functionality and test modes through simulation.

·        Work closely with design, physical design, and verification teams for DFT signoff.

Silicon Bring-up & Production Support

·        Support first silicon bring-up and failure analysis.

·        Collaborate with ATE teams for production test development.

·        Debug manufacturing test issues and improve yield.

Cross-Functional Collaboration

·        Interface with Architecture, RTL Design, Physical Design, STA, and Product Engineering teams.

·        Participate in design reviews and contribute to DFT methodology improvements.

Required Skills

Technical Skills

·        Strong understanding of:

o   Scan Architecture

o   Scan Compression

o   ATPG

o   MBIST/LBIST

o   JTAG/Boundary Scan

o   Fault Modeling

o   DFT Signoff Methodologies

EDA Tools

Experience with one or more:

·        Synopsys DFT Compiler

·        Synopsys TestMAX / TetraMAX

·        Cadence Modus

·        Siemens Tessent Scan

·        Tessent MBIST

·        Tessent Diagnosis

Languages & Scripting

·        Verilog/SystemVerilog

·        TCL

·        Perl

·        Python

·        Unix/Linux Shell Scripting

Debug Skills

·        Scan chain debugging

·        ATPG pattern analysis

·        Silicon failure diagnosis

·        Coverage closure

Preferred Qualifications

·        Experience on Qualcomm Snapdragon, Automotive, AI/ML, DSP, or Modem SoCs.

·        Exposure to low-power DFT methodologies.

·        Knowledge of UPF/CPF and power-aware testing.

·        Understanding of advanced-node designs (7nm, 5nm, 4nm, 3nm).

·        Prior silicon bring-up and yield improvement experience.

Education

·        Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related field.

Keywords

DFT, Scan Insertion, ATPG, MBIST, LBIST, JTAG, Boundary Scan, Tessent, Modus, DFT Compiler, TestMAX, Silicon Bring-up, OCC, Compression, Fault Coverage, SoC, Qualcomm, Snapdragon.

Role

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.

Designation

Associate